Previous DMOS transistors have a cell array formed as homogeneously as possible. Since slight manufacturing fluctuations are always present, however, the cells of a large cell array are never perfectly identical. This has the effect that in operating states in which instances of current splitting can occur, such as, for example, in applications in linear controllers (SOA area) or in the case of avalanche effects (switch-on of the parasitic bipolar transistor or temperature increase up to intrinsic conduction), the most unfavorable (weakest) cells always form the current filament in a very locally delimited manner. In this case, the precise location of the occurrence of the weakest cell or of the current filament is not predictable and is thus statistically randomly distributed in the large cell array.
In order to form an overload protection for power transistors, previous concepts provide temperature or current sensors positioned at the edge or centrally in the cell array of the power transistor. Since, in most planar components, for example diodes or bipolar transistors of temperature sensing devices, both fully blocking edge terminations of the power transistor cell array and of the temperature sensing structure and an additional guard ring are necessary in order that the transistor cell array and the temperature sensing structure are not coupled electrically but rather only thermally. The customary temperature sensing device and the cell array in which the heat is generated are usually at a distance of approximately 70 to 100 μm from one another. This has the consequence that a large temperature gradient builds up over this distance and, as a result, rather than the true temperature in the cell array, a significantly lower temperature is detected in the temperature sensing device. This in turn frequently leads to delayed turn-off, so that the component is either already totally destroyed or incurs damage leading to reliability problems.
In order to improve this situation, DE 38 31 012 A1 proposes positioning a polysilicon resistor as temperature sensing device as centrally as possible in the cell array. Proximity to the heat source is directly afforded here. However, the polysilicon resistor, if it is formed in a trench, is subject to large manufacturing fluctuations in the region of approximately ±30%, so that it is necessary here to work with a reference polysilicon resistor in the edge region of the chip. This requires additional space, causes further costs and can also only ever detect relative changes in temperature between chip edge and cell array. If operating conditions are present which heat the cell array relatively slowly (for example over several 100 μs), then the chip edge is also no longer at the cold reference temperature, but is also already heated to an unknown extent. This results in great uncertainty with regard to the “true” temperature in the cell array.
By virtue of the instances of current splitting described above, a temperature sensor positioned in the cell array always has the major disadvantage that a current filament that occurs randomly somewhere in an unpredictable manner in the cell array is detected only with a very great delay or is not detected at all by said temperature sensor, as a result of which the component can no longer be turned off in a timely manner and is destroyed.
The present invention provides an effective overload protection for field effect power transistors which can very rapidly detect the reaching of a critical temperature/of a critical current intensity, so that the power transistor can be turned off in a timely manner prior to its thermal self-destruction, even when the potential location of overheating (current splitting) is inhomogeneous and occurs statistically in the cell array.